MANIFEST.in
README.md
setup.py
pythondata_cpu_serv/__init__.py
pythondata_cpu_serv.egg-info/PKG-INFO
pythondata_cpu_serv.egg-info/SOURCES.txt
pythondata_cpu_serv.egg-info/dependency_links.txt
pythondata_cpu_serv.egg-info/not-zip-safe
pythondata_cpu_serv.egg-info/top_level.txt
pythondata_cpu_serv/verilog/.gitmodules
pythondata_cpu_serv/verilog/LICENSE
pythondata_cpu_serv/verilog/README.md
pythondata_cpu_serv/verilog/serv.core
pythondata_cpu_serv/verilog/servant.core
pythondata_cpu_serv/verilog/serving.core
pythondata_cpu_serv/verilog/bench/servant_sim.v
pythondata_cpu_serv/verilog/bench/servant_tb.cpp
pythondata_cpu_serv/verilog/bench/servant_tb.v
pythondata_cpu_serv/verilog/bench/uart_decoder.v
pythondata_cpu_serv/verilog/data/alhambra.pcf
pythondata_cpu_serv/verilog/data/arty_a7_35t.xdc
pythondata_cpu_serv/verilog/data/cyc1000.sdc
pythondata_cpu_serv/verilog/data/cyc1000.tcl
pythondata_cpu_serv/verilog/data/icebreaker.pcf
pythondata_cpu_serv/verilog/data/lx9_microboard.ucf
pythondata_cpu_serv/verilog/data/nexys_a7.xdc
pythondata_cpu_serv/verilog/data/pipistrello.ucf
pythondata_cpu_serv/verilog/data/tinyfpga_bx.pcf
pythondata_cpu_serv/verilog/data/ulx3s.lpf
pythondata_cpu_serv/verilog/data/upduino2.pcf
pythondata_cpu_serv/verilog/data/zcu106.xdc
pythondata_cpu_serv/verilog/riscv-target/serv/compliance_io.h
pythondata_cpu_serv/verilog/riscv-target/serv/compliance_test.h
pythondata_cpu_serv/verilog/riscv-target/serv/link.ld
pythondata_cpu_serv/verilog/riscv-target/serv/makehex.py
pythondata_cpu_serv/verilog/riscv-target/serv/device/rv32i/Makefile.include
pythondata_cpu_serv/verilog/rtl/serv_alu.v
pythondata_cpu_serv/verilog/rtl/serv_bufreg.v
pythondata_cpu_serv/verilog/rtl/serv_csr.v
pythondata_cpu_serv/verilog/rtl/serv_ctrl.v
pythondata_cpu_serv/verilog/rtl/serv_decode.v
pythondata_cpu_serv/verilog/rtl/serv_mem_if.v
pythondata_cpu_serv/verilog/rtl/serv_params.vh
pythondata_cpu_serv/verilog/rtl/serv_rf_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_ram.v
pythondata_cpu_serv/verilog/rtl/serv_rf_ram_if.v
pythondata_cpu_serv/verilog/rtl/serv_rf_top.v
pythondata_cpu_serv/verilog/rtl/serv_shift.v
pythondata_cpu_serv/verilog/rtl/serv_state.v
pythondata_cpu_serv/verilog/rtl/serv_top.v
pythondata_cpu_serv/verilog/servant/ecppll.v
pythondata_cpu_serv/verilog/servant/ice40_pll.v
pythondata_cpu_serv/verilog/servant/servant.v
pythondata_cpu_serv/verilog/servant/servant_arbiter.v
pythondata_cpu_serv/verilog/servant/servant_clock_gen.v
pythondata_cpu_serv/verilog/servant/servant_ecp5.v
pythondata_cpu_serv/verilog/servant/servant_ecp5_clock_gen.v
pythondata_cpu_serv/verilog/servant/servant_gpio.v
pythondata_cpu_serv/verilog/servant/servant_lx9.v
pythondata_cpu_serv/verilog/servant/servant_lx9_clock_gen.v
pythondata_cpu_serv/verilog/servant/servant_mux.v
pythondata_cpu_serv/verilog/servant/servant_ram.v
pythondata_cpu_serv/verilog/servant/servant_ram_quartus.sv
pythondata_cpu_serv/verilog/servant/servant_timer.v
pythondata_cpu_serv/verilog/servant/servant_upduino2.v
pythondata_cpu_serv/verilog/servant/servclone10.v
pythondata_cpu_serv/verilog/servant/servclone10_clock_gen.v
pythondata_cpu_serv/verilog/servant/service.v
pythondata_cpu_serv/verilog/servant/servis.v
pythondata_cpu_serv/verilog/servant/servis_clock_gen.v
pythondata_cpu_serv/verilog/servant/servix.v
pythondata_cpu_serv/verilog/servant/servix_clock_gen.v
pythondata_cpu_serv/verilog/servant/servus.v
pythondata_cpu_serv/verilog/servant/servus_clock_gen.v
pythondata_cpu_serv/verilog/serving/serving.v
pythondata_cpu_serv/verilog/serving/serving_arbiter.v
pythondata_cpu_serv/verilog/serving/serving_mux.v
pythondata_cpu_serv/verilog/serving/serving_ram.v
pythondata_cpu_serv/verilog/sw/Makefile
pythondata_cpu_serv/verilog/sw/blinky.S
pythondata_cpu_serv/verilog/sw/blinky.hex
pythondata_cpu_serv/verilog/sw/link.ld
pythondata_cpu_serv/verilog/sw/makehex.py
pythondata_cpu_serv/verilog/sw/zephyr_hello.hex
pythondata_cpu_serv/verilog/sw/zephyr_hello_mt.hex
pythondata_cpu_serv/verilog/sw/zephyr_phil.hex
pythondata_cpu_serv/verilog/sw/zephyr_sync.hex